The University of California San Diego has been awarded $11.3 million over four years from DARPA to lead a multi-institution project which aims to develop electronic design automation tools for 24-hour, no-human-in-the-loop hardware layout generation.
The project, called OpenROAD (Foundations and Realization of Open, Accessible Design), supports the Intelligent Design of Electronic Assets (IDEA) program within DARPA’s larger Electronics Resurgence Initiative (ERI). ERI is led by DARPA’s Microsystems Technology Office (MTO), and aims to address the impending engineering and economic challenges now confronting the advancement of microelectronics after 50 years of relentless progress.
Professor Andrew Kahng from the UC San Diego Jacobs School of Engineering will serve as director of the OpenROAD project, which addresses the challenges to hardware and chip design today, including the cost and expertise required to develop cutting-edge integrated circuits. Kahng is on the faculty of both the Department of Computer Science and Engineering and the Department of Electrical and Computer Engineering at the UC San Diego Jacobs School of Engineering, where he holds the Endowed Chair in High-Performance Computing.
“For the U.S. to be the vanguard of innovation we need to fully leverage semiconductor technology,” Kahng said. “There’s an incredible delta between what’s possible with silicon versus what people are actually able to afford or bring themselves to risk attempting—we’re trying to narrow that gap.”
Kahng and his collaborators plan to do that by creating a fully automated, no-human-in-the-loop circuit layout generator that enables a larger universe of users to design electronic hardware and systems-on-chips within 24 hours, without sacrificing power, performance or quality. This will unleash a new era of circuit and system innovation.
Currently, designing and verifying integrated circuit chips requires large teams of designers using complex computer-aided design tools for upwards of a year to perform chip floorplanning, device placement and routing—with different specialists and tool chains required for integrated circuits, systems-in-package and printed circuit boards. Research teams, small companies and Department of Defense researchers often don’t have the human resources needed to even attempt such a daunting design task. Moreover, many organizations are priced out of integrated circuit design, putting a drag on innovation.
“Chip design today is a 24/7 job—and when extremely sophisticated design tools finish their task, there can still be thousands of errors and rule violations that someone has to sit down and manually fix,” said Dennis Sylvester, a professor at the University of Michigan and co-investigator on the OpenROAD project. “That’s why this whole idea of developing a chip in 24 hours with no humans is so audacious. We’re swinging for the fences in so many ways.”
To accomplish their vision, the OpenROAD team will apply machine learning, extreme levels of design partitioning, cloud-based optimization, and restricted layout methodologies to tame the complexities of hardware design tools and the hardware design process.
Machine learning algorithms will allow tools to adapt and self-tune, such that the design flow will get smarter each time it’s used, resulting in better-optimized designs. Machine learning will also contribute to more effective ways of partitioning the layout problem into smaller segments that can be processed in parallel, in order to meet the 24-hour requirement. Such extreme partitioning approaches are not used today because optimization is degraded at the interfaces of these segments.
“If you want to finish in 24 hours, you have to free yourself from several long-standing mindsets,” Kahng said. “We simply have to accept fragmentation as a requirement, and then figure out how to perform high-quality design optimization within that constraint. Parallel and cloud-based approaches will be essential here.”
Setting bounds or restrictions on the layout of the chip will also be part of OpenROAD’s approach to chip design, meant to provide “freedom from choice” and establish protocols for layout implementation based on the design goals specified by the user.
“We’re viewing chip design as a process with clearly bounded resources: time, computers, tool licenses, and so on. No one has really studied how to orchestrate tools to optimize chips while staying within a fixed box of those resources. No one knows how to optimize chip design to finish within a certain amount of time while safely avoiding any human interventions. This is a fundamentally new paradigm we’re developing,” Kahng said.
In addition to the new technical approaches Kahng and his team are using to solve the chip design challenge, OpenROAD also has a goal of creating new sharing mindsets within the hardware development community. The design tools and methodologies produced by OpenROAD will be open-sourced in an effort to democratize hardware innovation, in the same way that open source software enabled innovation at the application level.
The OpenROAD Team
The OpenROAD team includes researchers from six universities—UC San Diego,the University of Michigan, University of Illinois at Urbana-Champaign, University of Texas at Dallas, University of Minnesota, and Brown University—along withQualcomm and Arm.
OpenROAD’s industry partners are collaborating with UC San Diego on the foundational technologies that underpin the project: machine learning, design partitioning and cloud-based optimization. Qualcomm is guiding simplifications of the design solution space and the identification of key metrics necessary to drive the 24-hour, autonomous design process. Arm is guiding development of machine learning models with system examples and calibrations for design outcomes.
On the university side, professor Lawrence Saul of UC San Diego will provide broad expertise in machine learning across the OpenROAD project. Three faculty from the University of Michigan-Professors Dennis Sylvester, David Blaauw and Ronald Dreslinskiwill lead OpenROAD’s “internal design team” that will specify tool functions and validate tool quality. University of Texas at Dallas professors Carl Sechen and Bill Swartz will create OpenROAD’s tools for detailed routing, layout finishing and placement. Professor Sherief Reda of Brown will develop the cloud infrastructure and logic synthesis. At the University of Minnesota, Professor Sachin Sapatnekar will develop tools and methodologies for parasitic extraction and power and signal integrity analysis. The University of Illinois effort, led by Professor Martin Wong, will contribute floorplanning and detailed routing capabilities. UC San Diego is responsible for timing analysis, placement, clock tree synthesis, and layout finishing. Numerous technical advisers from leading technology companies are also expected to provide technical contributions as the team aims to make the 24-hour, automated chip design process a reality, and deliver a digital integrated circuit layout flow to the larger ERI effort.