CEA-Leti and Silvaco Team Up!
Project Combines CEA-Leti's Semiconductor Development Expertise and Silvaco's SPICE Simulation and Variability Analysis Technologies. LAS VEGAS - June 3, 2019 - Leti, a research institute of CEA-Tech, and Silvaco Inc., a leading global provider of software, IP and services for designing chips and electronic systems for semiconductor companies, today announced, during the 56th Design Automation Conference (DAC) in Las Vegas, a project to estimate and model the yield of ultra-low-voltage (ULV), ultra-low-leakage (ULL) static random access memory (SRAM) used in computing applications. Accurate yield prediction in the early stage of the IC design cycle lowers manufacturing costs and improves quality. Variability in manufacturing is highly detrimental to mass production yield of silicon chips with large memories, such as embedded caches. The Accelerated Simulation of Array for Yield Assessment (ASAYA) Project at CEA-Leti aims to validate the estimates based on electrical SPICE circuit simulations against silicon results after manufacturing. The challenge is to assess whether low failure rates (in the order of one failure in 1 billion) observed in simulation guarantee acceptable production yields for SRAMs above the MB range. In the past, such failures could be investigated successfully through classical Monte Carlo-based electrical simulation of bitcells, which allowed estimations with sufficient precision of the immunity margin against failures; or through the quasi-Monte Carlo method, which consists in evaluating the margin as a "number of sigmas," assuming its distribution follows Gauss's law.
